Regviz

Alif Semiconductor /AE512F80F55D5AS_CM55_HP_View /DSI /DSI_PHY_TMR_LPCLK_CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as DSI_PHY_TMR_LPCLK_CFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Alif Semiconductor/AE512F80F55D5AS_CM55_HP_View/DSI/DSI_PHY_TMR_LPCLK_CFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PHY_CLKLP2HS_TIME0PHY_CLKHS2LP_TIME

Description

Clock Lane Timer Configuration Register

Fields

PHY_CLKLP2HS_TIME

This field configures the maximum time that the D-PHY clock lane takes to go from low-power to high-speed transmission measured in LANEBYTECLK cycles.
PHY_CLKHS2LP_TIME

This field configures the maximum time that the D-PHY clock lane takes to go from high-speed to low-power transmission measured in LANEBYTECLK cycles.

Links

()

Register License

THIS SOFTWARE IS PROVIDED “AS IS”. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. ALIF SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data